Articles on Voltage Controlled Oscillators

This paper investigates the implementation of a Frequency Locked Loop (FLL) over a VCO. The FLL decreases phase noise and linearizes the transfer function. The FLL is fabricated on a 0.35um BiCMOS process and has an operation frequency of 10 GHz. 

This Article goes over the design of a VCO using Ansoft Designer. The VCO has an oscillation frequency of 1800 MHz +/- 30 MHz, an output power of 4 dBm, a voltage supply of 3 V and a Current consumption of 8 mA. 

A low phase noise VCO has been demonstrated using a harmonically tuned LC Resonance tank. The VCO has an operating frequency of 1 GHz and a Phase noise of -111 dBc/Hz at 100 KHz offset. The VCO has been fabricated on a 0.35um CMOS process.

This Article goes over the Design of a Clapp oscillator, using a varactor tuned ceramic coaxial resonator for voltage control of the output frequency. The frequency under consideration will be around 1.4 GHz. Includes some Small & Large Signal Design Techniques.

This paper describes design techniques for both single-ended and differential VCOs, with examples shown fabricated in GaAs MMIC processes. The potential uses and advantages of the differential over the conventional single-ended approach are discussed.

This Design Note explains a practical technique that can be used to reduce power supply noise in VCOs.