Analog Devices, a global designer and manufacturer of analog, mixed signal, and DSP integrated circuits has launched the ADRV9029, a highly integrated, radio frequency (RF) agile transceiver. The ADRV9029 offers four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. It provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.
ADRV9029’s receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with a wide dynamic range. Its four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. It also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.
ADRV9029’s complete transceiver subsystem includes automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated into this transceiver.
To achieve a high level of RF performance, ADRV9029 includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.
A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through its digital control interface.
ADRV9029 contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables the use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.
The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.
This transceiver has a serial data interface that consists of four serializer lanes and four deserializer lanes. ADRV9029’s interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. This interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. It supports both fixed and floating-point data formats. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.
Analog Devices' ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. It has comprehensive power-down modes included to minimize power consumption in normal use. The ADRV9029 is available in a 289-ball chip scale ball grid array (CSP_BGA) package that measures 14 × 14 mm and is ideal for 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations applications.
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