Interview with David Brubaker from Xilinx

  • David Brubaker - Zynq UltraScale+ RFSoC Product Line Manager

everything RF Interviewed David Brubaker, Zynq UltraScale+ RFSoC Product Line Manager, Xilinx. He believes the product will enable architectural shifts in wireless, wired, and A&D markets by enabling higher integration levels, smaller size, and lower system power consumption.   

David most recently held positions in Strategic Marketing and Business Development for the Wireless Business Unit, Programmable Solutions Group at Intel Corporation. There he focused on 4G and 5G radio and baseband solutions for tier-1 customers.

Before joining Altera/Intel, David spent 12 years at Texas Instruments in two leadership positions: Product Line Manager for Digital Radio Products and WLAN Engineering Manager. In the Digital Radio PLM role, he oversaw the development of two generations of Crest-Factor Reduction (CFR) and Digital Pre-Distortion (DPD) products. As Engineering Manager, he led the development of first generation 802.11 ag RF and baseband products, including reference designs for turn-key high-volume manufacture.

Earlier in his career, he held RF and wireless engineering leadership positions in several companies.

Brubaker holds a Master’s degree in Electrical Engineering from Santa Clara University and a Bachelor’s degree in Physics from San Diego State University.

Q. Can you give us a brief history of Xilinx?

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies – from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future. For more information, click here.

Q. When did you enter the RF SoC Business? What made your enter this area and what was your objective?

Development of wireless class data converters began in 2012 with several test chips and architecture improvements leading to the RF Data converter IP in the Zynq UltraScale+ RFSoC. Once the data converter IP was ready it was integrated into the Zynq UltraScale+ MPSoC family to leverage Xilinx 16nm family. The first Zynq UltraScale+ RFSoC was announced in 2017 and released to full production in 2018.

The decision to enter this area resulted from several factors. First Wireless is one of the largest markets for FPGAs and every wireless system has high-performance data converters that are usually connected to an FPGA or another digital device via an interface standard JESD204C. The JESD204C interface uses significant power and requires board area to implement. Integrating data converters in FPGA is a logical business decision, but historically difficult since data converters and FPGA were on different process nodes. Xilinx had to develop the data converter IP on the digital process node to enable integration. Second, the 5G wireless standard implements a radio architecture called Massive MIMO (Multiple-Input Multiple-Output) to increase system capacity.

Massive MIMO systems require a large number of antennas, each requiring a dedicated data converter and connection to an FPGA. Systems from 32 up to 256 antennas are common; the physical implementation of systems with separate data converters is challenging and the JESD204C power consumption is significant. By integrating the data converters in the FPGA, Xilinx can provide a smaller footprint and lower power consumption, both key needs for Massive MIMO systems. The result is the Zynq UltraScale+ RFSoC which provide customers with significant system implementation advantages over a discrete solution.  

Q. Can you Tell Us about Xilinx's Single-Chip Adaptable Radio Platform?

Xilinx Single Chip Adaptable Radio Platform, otherwise known as Zynq UltraScale+ RFSoC, consists of two key IPs integrated into Xilinx Zynq UltraScale+ MPSoC family: first: RF class data- converters mentioned above and Soft-Decision Forward-Error Correction (SD-FEC) block. Both of these IPs are highly configurable and able to support multiple markets and solutions by user configuration. For example, the ZU+ RFSoC can be used in 3G, 4G or 5G radio systems, microwave backhaul and DOCSIS systems to name a few.

Q. What is the Advantage of using the Xilinx RF SOC over other conventional approaches?

The primary advantages are reduced power and footprint (50 to 75%) and the flexibility to implement multiple radio solutions with one device. For example, by using RF sampling data converters customers can remove fixed analog filters required by discrete implementations, enabling systems that support multiple bands and standards without any changes to the hardware platform.

Q. What are the Key Target Markets and Applications for which it can be used?

The Zynq UltraScale+ RFSoC has broad applicability across multiple markets. Wireless radio and baseband are the largest but with significant additional markets in Phased Array Radar, Cable Remote PHY and Test and Measurement.

Q. Up to what frequency do the RF SOC Solutions Operate?

The Zynq UltraScale+ RFSoC currently has three generations: 1, 2 and 3.

  • Generation 1 supports up to 4GHz RF input/output,
  • Generation 2 supports up to 5GHz RF input/output,
  • while Generation 3 supports up to 6GHz RF input/output.

Q. What is the roadmap of the RF SOC Family? Are you planning to go higher up in Frequency?

At Mobile World Congress 2019 we announced the 2nd and 3rd Generation families and schedules. The supported frequencies of these families are listed above. The 2nd generation is sampling now and will be released to production in June of 2019. The 3rd Generation will sample in Q4 of 2019 and be full production in August of 2020. At the Xilinx Developer forum (XDF) in October 2018, we announced our new 7nm platform: Versal which will have a RF Sampling Version called AI RF. The Versal AI RF is still in planning but it will have higher RF input/output and sample rates.

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