AWR Version 16 Accelerates RF to mmWave 5G System Design and Analysis

AWR Version 16 Accelerates RF to mmWave 5G System Design and Analysis

Cadence announced the new version (V16) of the AWR Design Environment® a couple of weeks ago. AWR Design Environment Version 16 has ground-breaking, cross-platform interoperability to support RF IP integration for heterogeneous technology development across Cadence Virtuoso®, Allegro® PCB, Spectre® simulation, and IC package design platforms, delivering up to a 50% reduction in turnaround time compared to competing workflows. The V16 further introduces seamless integration with Clarity™ 3D Solver and Celsius® Thermal Solver, delivering unconstrained capacity for electrothermal performance analysis of large-scale and complex RF systems.

The Cadence® AWR Design Environment® platform provides RF/microwave engineers with integrated high-frequency circuit (Microwave Office®), system (Visual System Simulator™), and electromagnetic (EM) simulation (AXIEM®/Analyst™) technologies and electronic design automation (EDA) to develop physically realizable electronics ready for manufacturing. It helps designers create RF/microwave IP with the aid of complex IC, package, and PCB modelling, simulation, and verification, and address all aspects of circuit behaviour to achieve optimal performance and reliable results for first-pass success.

With AWR Design Environment V16, Cadence addresses RF/Microwave design and integration through the company’s Intelligent System Design™ strategy, which delivers computational software capabilities across all design elements of electronic systems. At the core of this strategy is design excellence, including an optimized EDA portfolio of tools with best-in-class RF, microwave, and mmWave circuit, system, and EM analysis, IP for semiconductor, package, and PCB design, and scalable access in the cloud.

Key features in V16 include:

  • Allegro integration: Ensures manufacturing compatibility and RF integration with PCB and IC package design flows.
  • Virtuoso integration: Leverages Microwave Office for RF front-end design IP and combines it with the Virtuoso Layout Suite for IC and module integration.
  • Clarity integration: Enables EM analysis for design verification of large RF structures such as module packaging and phased-array feed networks.
  • Celsius integration: Provides thermal analysis for monolithic microwave IC (MMIC) and PCB high-power RF applications.
  • AWR enhancements: Accelerates RF IP creation with advances in design automation and finite-element analysis (FEA) solver performance.

"Cadence platforms such as the AWR Design Environment, Allegro PCB/SiP, and Virtuoso RF with integrated EM solver technologies are critical to the development of our RF/mmWave MMIC, RFIC and multi-chip 2.5/3D packaging technology,” said Florian Herrault, Group Leader, Advanced Packaging Solutions at HRL Laboratories. “Our design team is very excited by the performance and productivity gains to be had through Cadence’s RF solutions. Having the ability to share RF IP created in Microwave Office with our IC, package and board teams is driving a significant reduction in our overall design time so we can deliver the highest quality products to market faster.”

Additional V16 release features include:

  • Parallel Remote Simulation: The job scheduler now supports multiple simultaneous remote queues, enabling designers to run long circuit simulation or optimization jobs in parallel, either locally or remotely. EM structures now support per-document remote queue selection and both Cadence AXIEM® planar EM and Analyst™ 3D finite-element method (FEM) simulations can be run on a remote Linux cluster.
  • Dynamic Voiding and Automatic Net Connectivity Extraction: A new dynamic voiding layout mode in Microwave Office software automatically adds clearance between layout shapes and nets for various drawing layers and is defined by constraint rules specified in the layout process file (LPF). Additional net management capability facilitates identifying net objects in layout and schematic, and a new connectivity mode enables automatic association of a shape to an overlapping net.
  • Version Control: Version control manages group design projects, allowing group design data management of complex, multi-function designs in many different technologies. It also prevents unintentional file overwriting when there are multiple users editing the same file in the version control database or central repository.
  • Layout Trace Interconnect Modelling: The new interconnect (INTERCONN) system block in Cadence Visual System Simulator™ (VSS) communications and radar systems design software models the effects of transmission line loss, impedance mismatch, and coupling. This block has five different operating modes to facilitate a design flow that begins with rough estimates of the layout, progressing to using final PCB layout traces in an EM simulation.
  • Simplex Optimizer: Enhanced single-thread and parallel simplex optimizers in Microwave Office software with variable step size provide more flexibility than previous simplex optimizers, making them more widely applicable and/or resistant to local minima.
  • RF Amplifier Power Saturation and Frequency Multiplier Modelling: Improvements to the VSS software’s modelling of RF amplifiers in saturation now yields a smoother power output versus power input curve. These improvements apply to time domain, RF budget analysis, and RF Inspector (RFI) simulations.
    In addition, the VSS software’s behavioural frequency multiplier models have been improved for both saturated output power and spur level, yielding close agreement between time domain, RF budget analysis, and RFI simulations. The predicted performance is less sensitive to input power variation, matching the behaviour of physical frequency multiplier devices.

The AWR V16 platform is now available for download. Click here for more information.

Publisher: everything RF