Skyworks Solutions has launched its latest portfolio of jitter attenuating clocks to resolve timing related issues in high-speed networking, communications and data center equipment that form the backbone of internet infrastructure. These new products are designed to meet the performance requirements of high-speed networks deployed to carry 5G traffic and support new applications like AI and edge computing. The new Si536x product family complements Skyworks’ current Si539x jitter attenuating clocks to suit the specific timing needs of designers and vendors.
Increasing demand for data bandwidth is driving the need for 400G/600G/800G+ Ethernet links using high-speed 56G/112G/224G PAM-4 SerDes and coherent optical technologies for internet infrastructure and data center environments. The Dell’Oro Group forecasts that these data rates currently comprise half of the total Ethernet data center, with 800G expected to dominate by 2025. These high-speed systems require multiple clocks at different frequencies, signaling formats and voltage levels with ultra-low jitter.
To address this need, the Si536x product family provides frequency flexibility and clock tree on-a-chip integration in a compact clock IC solution with up to 18 clock outputs featuring <55 fs RMS jitter, enabling optimal transceiver performance. The increased jitter margin also helps de-risk product development and accelerate time to market for networking equipment vendors.
“Skyworks’ latest product family continues the company’s long-standing history of developing innovative timing solutions, featuring its ultra-low jitter DSPLL architecture with MultiSynth ‘any-frequency’ clock synthesis,” said James Wilson, vice president and general manager of timing products at Skyworks. “These products address the next generation of high-speed communications’ designs, allowing our customers to take advantage of the highest performance, lowest jitter clocks available.”
Key Features of the Si536x Product Family
- Up to 18 outputs with any combination of frequencies up to 2.75 GHz and a wide range of selectable output formats, including LVPECL, LVDS, CML, HCSL and LVCMOS. These output thresholds are also customizable to support chipsets that have non-standard formats.
- Seamless input clock management with exceptional input reference clock switching performance, including internal and external hitless switching modes of operation, supporting 35 ps and 75 ps phase transients respectively.
- Full suite of clock quality metrics and alarms providing full visibility to clock fault monitoring.
- Best-in-class < -90 dB power supply rejection, enabling designers to reduce noise filtering components leading to a more cost-efficient solution and simplified bill of materials.
- In-circuit reconfigurability enabling output frequency changes on the fly system downtime.
Designers can quickly configure clock tree designs with Skyworks’ ClockBuilder Pro software. Using the intuitive ClockBuilder Pro with integrated design-rule checks, power consumption estimates and crosstalk wizard, designers can quickly generate complex device configurations in less than ten minutes, minimizing software development overhead.
Click here to learn more about Skyworks' latest jitter attenuating clocks.