The Impact of Final Plated Finishes on Insertion Loss for High Frequency PCB’s

  • Date:  November 9, 2017
  • Event Time: 8am PT / 11am ET

Webinar Overview

Abstract:
There are many different final plated finishes used in the PCB industry and each have their own concerns related to insertion loss. The impact of loss for an applied finish is generally dependent on frequency, circuit thickness and design configuration. The design considerations in this webinar will be microstrip transmission line circuits and grounded coplanar waveguide (GCPW) transmission line circuits. Loss vs. frequency data will be given for these circuit configurations, considering five different plated finishes commonly used in the PCB industry. Additionally, circuit insertion loss is substrate-thickness-dependent and circuits using different substrate thicknesses will be evaluated considering the impact on insertion loss using different plated finishes.

To ensure a more thorough understanding for the effect of plated finish on insertion loss, this webinar will be split in two categories. The first category will give circuit results from PNA measurements in the band of microwave and lower millimeter-wave frequencies and the second category will demonstrate the use of electromagnetic (EM) modeling software (Sonnet Software) yielding results which correspond to the measured data.

Sonnet Software is a 3D planar EM software with extreme accuracy by employing Green’s function and yielding results to full numerical precision. The software is well-known for its user friendly interface and has the ability to model the impact of final plated finish influences on insertion loss with ease. A new technique will be demonstrated which greatly simplifies the formation of circuit geometry, with the added metal finish, for proper modeling of the impact plated finish has on RF performance. The webinar will be structured as follows:

  • Basic overview of insertion loss
  • How final plated finish impacts insertion loss for microstrip and GCPW structures
  • Illustration and discussion of measured results
  • Description of a basic plated finish model in Sonnet
  • Introduction to SonnetLab, the Sonnet/MATLAB scripting interface
  • Demonstration of applying plating to a circuit with SonnetLab

Final plated finishes are necessary for most high frequency circuit applications and it is important for the designer to understand how insertion loss can be affected by final plated finishes. This webinar will give the designer sufficient information to be well prepared for designing circuits with adequate compensation for the effects of final plated finish on RF performance.

Presenter Bios:

John Coonrod is the Technical Marketing Manager for Rogers Corporation, Advanced Connectivity Solutions Division. John has 30 years of experience in the Printed Circuit Board industry. About half of this time was spent in the Flexible Printed Circuit Board industry regarding circuit design, applications, processing and materials engineering. The past fifteen years have been spent supporting High Frequency Circuit materials involving circuit fabrication, providing application support and conducting electrical characterization studies. John is the Chair for the IPC D24C High Frequency Test Methods Task Group and holds a Bachelor of Science, Electrical Engineering degree from Arizona State University.

Dr. Brian Rautio is the Vice President of Operations for Sonnet Software, Inc. He received the B.S.E.E. degree from Rensselaer Polytechnic Institute in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Syracuse University in 2014, where his algorithm research helped him to win the All-University Doctoral Prize. Brian has been a member of IEEE since 2005, having previously volunteered for the IMS2012 steering committee and MTT AdCom, and is currently a reviewer for the MTT Transactions. He is also a member of the Eta Kappa Nu electrical and computer engineering honor society.