Getting the Most Out of DDR4 and Preparing for DDR5

  • Date:  Tuesday, April 24, 2017
  • Time: 1:00 PM ET | 10:00 AM PT

Webinar Overview

DDR4 was the first DRAM technology to break the High Speed Digital paradigm, focused on signal timing and Voh/Vol/Vih/Vil-based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds were replaced by eye diagrams, bit error rates, and statistical analysis of random jitter/noise, thus closing a gap between the DDR specification and the behavior of real systems. Many memory designers are still climbing this learning curve, attempting to get the best performance from DDR4 designs at minimum design risk/cost.

Right on the heels of DDR4, DDR5 reaches speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This webinar will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. We will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.

Webinar Presenter
Perry Keller
Memory Applications Program Manager
Keysight Technologies

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