Build Your RF PCB to Specs and Improve Yield 10x Faster

  • Webinar Date

    August 23, 2018

  • Webinar Time

    10am PT / 1pm ET

Webinar Overview

Why This Webcast is Important:
Are you spending days trying to optimize your selection of commercial RLC (resistor-inductor-capacitor) SMT parts so that you can quickly build your RF PCB to meet specs and yield? Now you can compensate for component parasitics and layout EM effects in one pass.

Automatic selection and optimization of RLC values
Accurate Modelithics scalable parasitic models
Automatic layout EM-circuit co-simulation
Yield analysis from chosen parts tolerance
Attend this 1 hour webinar to stay relevant with the latest development in RF PCB design. Knowledge gained from this seminar will save you frustration and your company many costly hardware and testing iterations.

Who Should Attend:
All RF Circuit designers who need to prototype and build RF PCBs.

How-Siang Yap, Genesys Product Manager, Keysight EEsof EDA
How-Siang Yap is the Genesys Product Manager at Keysight EEsof EDA. Over the past 25 years in the microwave component and RF EDA industry, he has held positions in R&D, semiconductor foundry relationship, technical product marketing, Asia-Pacific regional EDA sales management and product management in DSO, HP, Agilent and Keysight Technologies. He has a 1st class honors BE from the University of New South Wales, Australia and an Executive MBA from the Helsinki School of Economics.

Eric O'Dell, Product Manager, Modelithics
Eric O’Dell is the Product Manager of Modelithics, Inc and has been with the company since 2008. Eric over sees the development of the Modelithics Library adding and encoding new models, expanding its functionality and migrating it into additional simulators. He has over 30 years of software application development experience and has worked in both the public and private sector for various companies including Eckerd, SPARTA and IBM. His experience includes a vast array of programming and scripting languages to develop applications ranging from simple bookkeeping databases to complex enterprise systems. Eric earned a B.S. Degree in Electrical Engineering in 1992 from the University of Alabama in Huntsville.

Rulon Vandyke, Lead R&D Engineer, Keysight EEsof EDA
Rulon Vandyke is the lead R&D engineer for Genesys RF synthesis and RF system simulation at Keysight EEsof EDA. He received a bachelor’s and master’s degree of Science in electrical engineering from Brigham Young University in 1990. For 10 years, he designed, first-, second-, and third-generation digital cellular transceivers and base stations for AT&T Bell Labs and Lucent Technologies. In 2001 he joined Eagleware Corporation and developed the RF architecture simulation tool called Spectrasys and WhatIF, a frequency planning tool for their product called Genesys. Since the acquisition of Eagleware in 2005 by Agilent Technologies, that later became Keysight Technologies he has lead the development of RF Architecture Simulation.