How to Reduce EMI in Switch-Mode Power Supplies with Post-Layout Simulation

  • Webinar Date

    Thursday, December 05, 2019

  • Webinar Time

    10:00 AM Eastern Standard Time

Webinar Overview

The need for greater efficiency, increased power density, and lower cost is driving the demand for high-speed switch-mode power supplies (SMPS). This trend results in new challenges, as the layout of a printed circuit board becomes a source of electromagnetic interference (EMI). Post-layout analysis of a “virtual prototype” is ideal for managing this challenge, but until now it required expertise with a complicated, general-purpose electromagnetic field solver. In this webinar, we show how Keysight’s PEPro software makes post-layout analysis as easy as pre-layout analysis. 


  • A higher-speed SMPS is smaller, lighter, and cheaper, but higher speeds introduce new challenges, such as unwanted EMI 
  • Suppression of EMI by traditional “solder-and-see” methods is costly, time-consuming, and nondeterministic 
  • In this webinar, we present a new method that is cost-effective, is faster and yields deeper insights — namely a series of “virtual prototypes” using post-layout simulation  


Dr. Colin Warwick
Power Electronics Product Manager
Keysight Technologies

Colin is a product manager for power electronics where his focus is on design and analysis tools for engineers building high di/dt switched-mode power supplies. Before joining Keysight, Colin was with Royal Signals and Radar Establishment in Malvern, England; Bell Labs in Holmdel, NJ; and The MathWorks in Natick, MA. He completed his bachelor, masters, and doctorate degrees in physics at the University of Oxford, England. He has published over 50 technical articles and holds thirteen patents.