Solving PCI Express 5.0 Test Methodologies & Measurement Challenges
Wednesday, December 11, 2019
2:00 PM Eastern Standard Time
The server/storage industry is rapidly progressing to PCIe Gen5 due to the increasing requirements imposed by cloud-based computing power, storage capacity, and network bandwidth. This rapid progression brings an entirely new set of test and measurement challenges for both base silicon testing and CEM compliance testing.
Our webinar will discuss how to solve some of the new test and measurement challenges for PCIE 5.0 at 32.0 GT/s.
The key topics covered in this presentation are as follows:
- PCI Express 5.0 Base Tx methodology and demonstrations of Tektronix software solutions.
- PCI Express 5.0 Motherboard TX methodology. Discuss pros and cons of different methodologies and Tektronix solutions.
- PCI Express 5.0 Base Rx Calibration methodology walkthrough and Tektronix software options.
Dan Froelich, Director of Systems Engineering and Domain Expert, PCIe, Tektronix Dan Froelich joined Tektronix in November 2018. For the prior 18 years Dan worked as an Intel engineer and architect focused on specification and compliance test methodology development for USB and PCI Express standards. Dan served as co-chair of the PCI-SIG electrical workgroup and technical editor for the electrical specification for the PCIe 4.0 and PCIe 5.0 specification development. Dan also served as chair of the PCI-SIG Card Electromechanical (CEM) workgroup and technical editor from 2005 to 2018 covering the PCI Express 2.0, 3.0, 4.0 and early 5.0 CEM specification development Dan Froelich graduated with honors and high distinction from Harvey Mudd College in 1996 with a BS in Physics. Dan holds 6 US patents with several more applications pending.
David Bouse, Systems Engineer, Tektronix
David Bouse recently joined Tektronix as a Systems Engineer in December 2018. Previously I was working on USB & PCIe Industry enabling with a focus on Tx/Rx Test methodologies, Waveform Post-Processing tools (SigTest), Test Fixture design, and test specification development.