Enabling 5G & Designing Wafer Level Chip Scale Packaging

  • Webinar Date

    Wednesday, March 25, 2020

  • Webinar Time

    11:00 AM Central European Time

Webinar Overview

Wafer-level chip-scale packaging (WLCSP) is attractive because it allows engineers to implement a very small package profile while minimizing interconnect lengths. Today’s WLCSPs are generally an afterthought in the design process. Engineers usually analyze and consider the effects only after completing the IC design. As complex 5G and automotive phased array systems move to higher mmWave frequencies (60 GHz), packaging effects begin to dominate performance, meaning the package design needs to become an integral part of the IC development process. This webinar will illustrate an approach to analyzing WLCSPs in real-time as part of the design process.

Key Learning

  • Current WLCSP design approaches 
  • The most common phased-array design challenges 
  • How to avoid the most common mmWave RFIC design failures