Circuit Extraction Techniques Provide Faster Interconnect Modeling and Analysis

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  • Author: Dr. Michael Heimlich
Communications designers develop-ing products with GHz frequencies and Gbps edge rates who are using traditional printed circuit board (PCB) sig-nal integrity (SI) solu- tions are finding that while their designs behave well under virtual prototype or simu-lation scenarios, they are failing when migrat-ed to build and test. Why? Because the design of the interconnects above 1 GHz is an increasingly important issue—no longer a sec-ond- or third-order effect that can be largely ignored. Due to both large-scale integration and higher operating frequencies, intercon-nects no longer operate as simple lumped RLC circuits and so the modeling and simulation of these high-performance and complex design inter-connections must be taken into account from the get-go. If not, designers find them-selves spending excessive time and money on redesigns and re-spins, and experimenting on the test bench, which adds cost to the final products not only with additional “fix-it” com-ponents, but ultimately in lost market window opportunities.