Testing FPGA-Based Hardware Emulators with Slow I/Q Signals
During the design process of chipsets or modules, FPGA-based hardware emulators are utilized to perform early tests with real test and measurement instruments. These hardware emulators usually run at artificially reduced speed, but apart from that function like the finished design. In this application note we explain how to test FPGA-based hardware emulators using Rohde & Schwarz vector signal generators for creating suitable real-time test signals at reduced sample rates. We further explain how to correctly adapt AWGN signal generation and fading simulation for “slow I/Q”.
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