Characterization of atomic layer deposition HfO2, Al2O3, and plasmaenhanced chemical vapor deposition Si3N4 as metal¡Vinsulator¡Vmetal capacitor dielectric for GaAs HBT technology

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  • Author: Jiro Yota, Hong Shen, and Ravi Ramanathan

Due to the increasing functionality and the demand for capacity, the die size in semiconductor wafer manufacturing must be reduced. Excluding the bond pad and scribe street areas, metal–insulator–metal (MIM) capacitor device, which is a key passive component in GaAs circuit designs, could consume up to 35% of the total die area.1,2 Therefore, it is critical to increase the capacitance density of the MIM capacitor in these designs, fabricated using GaAs process technologies, including GaAs heterojunction bipolar transistor (HBT) technology. Increasing the capacitance density of the MIM capacitors will allow the reduction of capacitor area in these designs, resulting in die size reduction. Furthermore, the higher capacitance density of these capacitors will allow the integration of additional off-chip capacitors on to the GaAs die, and thereby reducing the bill-of-materials in a multichip module.