Evaluation of Material and Process Contributions to BiFET Variation Using Design of Experiments

In this paper we present a method to separate the impact of feature size variation and material/gate etch variation in field effect transistors (FETs) manufactured in our BiFET process. The key to this separation is the realization that material and gate etch variation move the Idss (zero bias drain current) and threshold voltage (Vp) along a line determined by Idss vs. Vp 2 while feature size variations break this correlation and move the Idss/Vp perpendicular to this line. This method of separation should also be applicable to understanding HEMT devices that use a power-recess.