Design Method for the Fastest Settling Type 2 Phase Lock Loop: Part 1

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  • Author: Akmarul Ariffin Bin Salleh
Fast settling time is always desirable in any PLL (phase lock loop), as long as the noise performance is within limit. One application where fast settling is of high importance is in the design of a network analyzer. A PLL is used to synthesize both the source signal for the device under test and the LO signal for down conversion. With a faster settling source and LO, more measurements can be done for a given period of time, thus improving measurement throughput. In a test environment, this improvement directly yields higher productivity, since more parts can be tested. In addition to that, faster sweep time in a network analyzer will enable a user to approach real time measurement to capture any intermittent signal or glitches.
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