EDA Tools for RFIC Design: Business and Product News

TSMC’s EM Tool Qualification Program assists IC designers by providing certified process technology files, layout and measurements for 65 nm and 90 nm process technologies. The program ensures greater accuracy of EM simulators and extractors used in applications such as high-speed digital clock circuits and high-frequency mixed-signal RF designs. Certified process files eliminate several error sources in the design process and enable designers to use Helic’s VeloceRF platform on TSMC 65 nm processes with confidence. Helic’s VeloceRF features a rapid and high-capacity, vector-based RLCK modeling engine that can generate very accurate models for any kind of integrated inductive component, and also includes a spiral inductor synthesizer. It eliminates the need for custom layout and eases adoption by foundries and design teams. Features such as conductor track slotting to mitigate metal stress, geometry resizing under current density constraints and the use of dummy fill patterns are pre-programmed in VeloceRF and are consistently supported by the layout and LVS modules.
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