JESD204B PHY Layer Compliance Test

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  • Author: By Maury Wood, Scott Ferguson, Joe Evangelista
In the second half of 2012, the first high speed data converters with 10 Gbps JESD204B serial interfaces will be introduced to the market. 10 Gbps per differential lane is nearly twice the bandwidth of the legacy LVDS DDR parallel interface that JESD204B makes obsolete. Digital radio transceiver design engineers have been quick to adopt this new SerDes-based digital interface, as the cost saving, the technical merits, and the ease-of-duced to the market. 10 Gbps per differential lane is nearly twice the bandwidth of the legacy LVDS DDR parallel interface that JESD204B makes obsolete. Digital radio transceiver design engineers have been quick to adopt this new SerDes-based digital interface, as the cost saving, the technical merits, and the ease-of-use value proposition is compelling. JESD204A lanes run up to 3.125 Gbps, which is relatively easy to implement in conventional PCB materials across 20 cm traces. JESD204B is defined with a maximum of 12.5 Gbps, which requires careful attention to PCB materials, design methods, and PHY layer compliance testing. In this paper, Agilent and NXP will provide guidance to design engineers intending to implement 10 Gbps - 12.5 Gbps JESD204B lanes, and will provide practical advice with respect to maximizing the TX (transmitter) eye opening at the RX (receiver) device. The potential need for TX pre-emphasis and RX equalization will be covered, as will newly proposed PHY layer complaint Method of Implementation (MOI) tests.