Simulation Results of Phase Noise of PLL Functional Blocks in 0.35 um SiGe Technology
This brief article presents results obtained from sim-ulation for the phase noise of the following common blocks in a PLL used for a 6.525 GHz fixed frequency source circuit. The simulation was done using the Advanced Design System from Agilent Technologies and based on a 0.35 μm, BiCMOS 60 GHz, SiGe process that pro-vides HBTs and CMOS transistors. Results of the work are presented in a graphical format. From these results the phase noise of the over-all PLL was estimated . Phase noise was analyzed from the center to 1000 kHz offset frequency.
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