The excellent phase noise exhibited in ADI’s latest generation of high speed DACs enables size, weight, power/performance, and cost benefits in next-generation low phase noise, fast hopping agile RF/microwave synthesizers. A challenge is that to achieve this DAC capability, the fixed DAC sample clock must have very low SSB phase noise that is beyond the capability of mainstream wideband VCO PLLs. A method employing an analog phase detector (PD) is offered in this article that can improve in-loop phase noise performance by 10 dB to 20 dB compared with conventional phase/frequency detector synthesizers. To meet the most demanding phase noise system requirements, the suggested fixed clock implementation is a dielectric resonator oscillator (DRO) locked using an analog PLL. Other more conventional examples are also provided in this article employing a commercially available MMIC VCO. This article explains the benefits of a DAC-based coarse/fine mixer microwave synthesizer with block diagrams, measured phase noise results, and also provides an application circuit so that the interested engineer can try this in the lab.
The aerospace & defense (ADEF) community has a justifiable obsession with phase noise. For example, radar, electronic warfare (EW), and a plethora of other applications require best-in-class phase noise performance from fast hopping frequency synthesizers and exciters. These frequency functional blocks often set critical system performance, such as radar clutter attenuation, and are used in larger frequency translation, tuner, and modulation schemes. ADI’s latest generation of high speed DACs exhibits extremely low additive phase noise that brings the long-standing dream of simplifying agile frequency generation architectures within reach. The evolution to DAC-based frequency synthesis enables much lower size, weight, power, and cost (SWaP-C) solutions replacing much larger, more expensive signal chains. In order to realize the phase noise potential, however, the system designer cannot use just any old sampling clock source scheme. This article explains the phase noise considerations and trade-offs when implementing a sample clock for best DAC phase noise. Taking things a step further, the article considers a low phase noise approach for implementing a wideband fast hopping synthesizer in the Ku-band to Ka-band range. An application circuit block diagram and measured data are provided so that designers can duplicate the experimental data on their bench and leverage the approach in their design.