Over the past several decades, wireless system channel counts and bandwidths have steadily increased. The driving factors for these modern telecommunication, radar, and instrumentation systems are their data rate and overall system performance requirements. However, these requirements have also increased power envelopes and system complexities, making power density and component-level features more important.
To help address some of these limitations, the semiconductor industry has integrated more channels on the same silicon footprint, thereby reducing watt per channel requirements. Additionally, semiconductor companies are integrating more complex features into digital front ends that ease the off-chip hardware design historically achieved in an application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) fabric. These features can range from generic components like filters, downconverters, or numerically controlled oscillators (NCOs), to more complex application-specific operations.
Signal conditioning and calibration problems only become more compounded when developing high channel count systems. This architecture may require unique filters or other digital signal processing (DSP) blocks per channel, thereby making the shift to hardened DSP more important for power savings.
This article presents experimental results utilizing a 16-channel transmit and 16-channel receive subarray in which all transmit and receive channels are calibrated using hardened DSP blocks within the digitizer integrated circuit (IC). The resulting multichannel system provides performance improvements in size, weight, and power when compared to other architectures. When comparing the resource utilization of an FPGA for the system, it becomes clear that the hardened DSP blocks solve significant challenges for designers of multichannel platforms.