New LDMOS Model Delivers Powerful Transistor Library—Part 1: The CMC Model
S. Wood and R. Pengelly, L. Dunleavy, W. Clausen, T. Weller and L. Emmad.
Last month, Part 1 of this article intro-duced the new CMC (Curtice/Model-ithics/Cree) non-linear LDMOS FET transistor model. The CMC model was described, and its utility demonstrated by making extractions on a 1 watt wafer-probeable FET. In Part 2, this device is used as the core of a 30 watt model to show the scalability to larg- er devices. The 30 watt model is built up by adding appropriate package parasitics and thermal model parameters to a scaled version of the 1 watt cell model and then validated against linear and non-linear measurement data. A 19 element high power transistor library based on the CMC model is also explained. This library covers devices of vari-ous power levels up to 90 watts and frequen-cies over the DC to 2.7 GHz range.
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