Measuring Seam/Crack Formation in Interconnect Metallization

Low cost processes, in both GaAs and Silicon, often use non-planar interconnect metals. While very efficient in simplifying processes, seam (more commonly called “crack”) formation due to inter-level dielectric topologies can cause significant thinning in the metallization, impacting the reliability and act as process defect that reduces circuit yield. To better understand and monitor crack formation, we used a series of test structures to develop an electrical test allowing crack formation to be characterized. We confirmed our results with cross sections. The methodology developed here is also used during the development of new process steps/processes to make sure the new process does not result in worse cracking and led to the identification of a design rule need in a process we were developing.