Design Trade-offs for High Linearity pHEMT Switches
Andrew Dearn, Liam Devlin
This paper describes design trade-offs for high linearity GaAs SPDT switches suitable for operation with low control voltages. Typical applications for such devices include GSM handsets and WLAN transceivers. Parameters investigated include gate topologies, the use of drain-source bypass resistors and the use of external reference voltages. At 1.9GHz the best performing of the family of switch designs yielded a typical insertion loss of 0.58dB, isolation of 21.3dB, +36dBm 1dB compression point, +53dBm input referred 3rd order intercept point, and harmonic levels less than -80dBc.
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