Low Latency Software Defined Radios for Point-to-Point Networks

Jun 29, 2020

There has been industry buzz around software defined radio (SDR) over the last several decades, however, older systems provided solutions for hobbyists with limited application in a commercial setting. Since then, many advancements in semiconductors and the overall technology powering SDRs, has made them more applicable for many commercial and mission critical applications.

Simply put, SDRs allow for two way wireless communication with integrated digital systems for flexibility. Recent advancements in SDR technology have enabled multi-channel transmit and receive solutions, flexible configurations, and integration capabilities, making these COTS systems the favored solution for many industries requiring a radio frequency (RF) component.

While these developments in SDR technology are relevant to a variety of markets, there is an often overlooked application of low latency, point-to-point networks. These networks have a tremendous benefit for distributed data transfers, civil & defense communications, and high frequency trading. Through the use of SDR, engineers of these applications are able to build fully integrated systems with the lowest latency – often resulting in lower latency than fiber.

These systems are capable of both the RF and digital aspects associated with communications. This includes a flexible radio chain for tuning, an FPGA for modulation/demodulation and additional DSP, and a high speed digital backhaul for passing any data to additional equipment (if needed). This integration of RF and digital components on the same platform results in an overall reduction in system latency.

The figure below illustrates a typical network which includes different locations for the transmit and receive equipment. At the transmit location, a host system is connected to the SDR and generates a payload to be transmitted. The SDR can offer additional DSP or waveform storage as required along with the transmission radio front end, pre-amplifier, amplifier, filters, and sample level attenuation control. If it is desired, and SDR can also provide simply the transmit radio front end and connect to additional equipment for amplification and filtering.

Fig. 1.1 where SDRs fit into the overall application - Block Diagram Tx

The end result is a connection to an antenna for analog transmission. On the receive side, the SDR is again connected to either a host system or another piece of networking equipment, and offers attenuation control, filters, receive radio chain, and optional DSP. Similarly to transmit, this can also be simplified to only providing the receive radio chain.

Fig. 1.2 where SDRs fit into the overall application - Block Diagram Rx

The overall latency in any analog to digital system includes several components with the specific contributors to latency within the SDR being; radio chain, converter, FPGA, DSP, packetization, buffering, network transmission, operating system, and application latency. This total latency can be summarized by the equations in Figure 2.1 and Figure 2.2, where τlat,Rx and τlat,Tx are the total receive and transmit latencies, τRF,Tx and τRF,Rx represent the transmit and receive group delays associated with the radio front ends, τADC and τDAC are the total converter (de)serialization delays, τDSP which is the DSP processing delay on the FPGA, and which accounts for Digital Up/Down Conversion, Decimation, Interpolation, and filtering, τbuf,Rx and τbuf,Tx represent the FPGA receive and transmit sample buffers, τdef rame and τf rame represent the time required for the FPGA to frame or deframe the Ethernet packets, τnet is the total network latency, (τos,Tx and τos,Rx) is the host PC operating system network stack latency, and τapp,Tx and τapp,Rx is the user space client receive or transmit latency.

Fig. 2.1 - τlat,Rx = τRF,Rx + τADC + τDSP + τbuf,Rx + τframe + τnet + τos,Rx + τapp,Rx

Fig. 2.2 - τlat,T x = τapp,Tx + τos,Tx + τnet + τdeframe + τbuf,Tx + τDSP + τDAC + τRF,Tx

It is of note that not all of these sources have consistent latency contribution. For example, the radio chain group delay is approximately constant, and largely invariant to changes in sample rate, or frequency, whereas network latency (especially transmit) and operating system latencies can be widely variable. There are steps system integrators can take to limit this variance, however consideration of this variance is highly important, particularly when transmitting at high sample rates across multiple channels.

As a default, most systems are not optimized for latency. The flexibility that an SDR provides a system allows for adaptations and programmability to provide latency optimization. The greatest non-deterministic contributors to latency are τos and τnet. Moving to a real time operating system (such as the real time Linux kernel), using the latest kernel drivers (to ensure optimal network card performance), and processor and core affinity provide the most immediate benefit. In addition, purchasing a network card optimized for low latency applications provides additional benefit.

It is also worth noting that the integration of the FPGA, and the option to embed application logic onto it, allows the SDR to connect directly to another network without the need for a dedicated host system. Through the SDR itself, there can be added reduction in network latency through the use of high throughput backhauls as available. 

Previously, it has been difficult to find commercially available solutions that meet the needs demanded of low latency network providers to avoid the need for costly and time consuming in-house development. Per Vices, a Toronto, Canada based SDR manufacturer, has COTS SDRs available that are optimized for low latency point-to-point links. These systems are deployed to power some of the fastest links around the world.

Click here for more information.

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Per Vices

Country: Canada
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