What is PCIe 6.0?

What is PCIe 6.0 or the sixth generation of Peripheral Component Interconnect Express?

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- everything RF

Jan 8, 2023

PCIe 6.0 is the sixth generation of the PCIe (Peripheral Component Interconnect Express) high-speed serial interface standard that is commonly used to connect peripheral devices such as Solid-State Drives (SSDs), hard disk drive, graphics cards, Wi-Fi cards, Ethernet hardware, and host adapters to the motherboard. PCIe standard was developed to replace the earlier PCI, PCI-X, and AGP parallel bus standards, by providing relatively higher data rates, wider bandwidths, and lower latency. PCIe 6.0 was announced on June 18, 2019 by the PCI-Special Interest Group (SIG), a group containing over 900 electronics and semiconductor companies that maintain conventional PCIe standards and specifications. 

The slots in PCIe can be configured to have either one lane or multiples of four lanes, such as x1, x4, x8, x12, and x16. A lane is an electrical signal path that consists of two differential signaling pairs with one pair for transmitting while the other for receiving data from other devices. Each signaling pair in a lane has two wires. Thus, a lane consists of four wires or signal traces. While the number of number of lanes can be increased to meet the data rate requirements of intended applications, each lande has the same bandwidth for any given PCIe version. PCIe 6.0 delivers a bit rate of 64.0 GT/s (Gigatransfers per second), which is roughly 8 GB/s per single lane (x1). This is double the bit rate offered by its previous version, PCIe 5.0 – 32 GT/s, which is approximately 4 GB/s per single lane (x1). Hence, a PCIe 5.0 x8 interface can be replaced by a PCIe 6.0 x4 interface that provides roughly the same amount of bandwidth.


This increase in data rate by a factor of 2 is due to the use of 4-level Pulse Amplitude Modulation (PAM) instead of Non-Return-to-Zero (NRZ) encoding scheme used in the eariler versions. By using PAM-4 as the line signaling coding technique, it is possible to transfer information at a rate of 2 bits per symbol period compared to 1 bit per symbol period as in NRZ scheme.

However, making this transition to PAM-4 scheme from the NRZ resulted in a relatively higher Bit Error Rate (BER) of 10-6 compared to NRZ that had a BER of 10-12. This is because the bits in the PAM-4 signal constellation are relatively closer than NRZ, thereby making it possible for two or more bits to overlap each other in the presence of noise. To resolve this issue, an error control algorithm - Forward Error Correction (FEC), is utilized in this version to detect and correct the bit errors occurring in routed lanes or channels. To further improve the link performance, a cyclic redundancy check (CRC) code is also used in conjunction with FEC scheme.

The PCIe 6.0 uses a special flow control unit (FLIT) signaling format for the data compared to PCIe 5.0 and other earlier versions that use an embedded clocking scheme with 128b/130b encoding format. The data packet for PCIe 6.0 has a size of 256 bytes that holds 242 bytes of data containing information from transaction layer (data size is variable) and a payload data from the data link layer. The remaining 14 bytes of data are reserved for error correction, ensuring data integrity.

In general, packet efficiency is defined by, 

Packet Efficiency =

PCIe 6.0 specification removes the additonal payload data or overhead from data link layer and the 128b/130b encoding format. This removal of overhead data and further modification due to the FLIT signaling format contributes to a relative increase in the packet efficiency compared to PCIe 5.0 and other earlier versions and simplified data management and processing.

A device that uses PCIe 6.0 interface also ensures backwards compatibility with all the earlier PCIe versions offering both hardware (mechanical interface) and software support. This means that PCIe 5.0 cards can work on motherboards that support PCIe 6.0 and vice-versa. However, by using PCIe 6.0 cards on PCIe 5.0 interface, the performance will be limited to PCIe 5.0. A slight tweaking in both hardware and software may be required to maintain or boost the performance.