What is SPI?

What is the SPI Interface? When is this interface used?

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Editorial Team - everything RF

Feb 26, 2021

Serial Peripheral Interface (SPI) is a synchronous serial communication interface that supports full-duplex mode where data can be sent and received simultaneously. It supports data transmission rates (>8Mbits) that are much faster/higher than UART and I2C. In SPI even if data/clock lines are shared between devices, each device will have a unique address wire. It is used in places where speed is important. For eg. SD cards, display modules or when info updates and changes quickly like thermometers).

SPI Communicates in 2 Ways:

  • The first is by selecting each device with a Chip Select line (CLK). A separate Chip Select line is required for each device.
  • The second is through daisy chaining where each device is connected to the other through its data out to the data in line with the next.

There is no limit to the number of SPI devices that can be connected. However, there are practical limits due to the number of hardware select lines available on the main device with the chip select method or the complexity of passing data through devices in the daisy-chaining method. In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex communication, which is simple and efficient.

Advantages of using the SPI Interface

  • The protocol is simple as there is no complicated slave addressing system like I2C.
  • It is the fastest protocol compared to UART and I2C.
  • No start and stop bits unlike UART which means data can be transmitted continuously without interruption
  • Separate MISO and MOSI lines which mean data can be transmitted and received at the same time

Disadvantages of using the SPI Interface

  • More Pin ports are occupied, the practical limit of several devices.
  • There is no flow control specified, and no acknowledgment mechanism confirms whether data is received unlike I2C
  • Uses four lines – MOSI, MISO, NCLK, NSS
  • No form of error check unlike in UART (using parity bit)
  • Only 1 master